R2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores

Florian Kriebel, Arun Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, Muhammad Shafique, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

On-chip last-level caches in multicore systems are one of the most vulnerable components to soft errors. However, vulnerability to soft errors highly depends upon the parameters and configuration of the last-level cache, especially when executing different applications. Therefore, in a reconfigurable cache architecture, the cache parameters can be adapted at run-time to improve its reliability against soft errors. In this paper we propose a novel reliability-aware reconfigurable last-level cache architecture (R2Cache) for multicore systems. It provides reliability-wise efficient cache configurations (i.e. cache parameter selection and cache partitioning) for different concurrently executing applications under user-provided tolerable performance overheads. To enable run-time adaptations, we also introduce a lightweight online vulnerability predictor that exploits the knowledge of performance metrics like number of L2 misses to accurately estimate the cache vulnerability to soft errors. Based on the predicted vulnerabilities of different concurrently executing applications in the current execution epoch, our run-time reliability manager reconfigures the cache such that, for the next execution epoch, the total vulnerability for all concurrently executing applications is minimized. In scenarios where single-bit error correction for cache lines may be afforded, vulnerability-aware reconfigurations can be leveraged to increase the reliability of the last-level cache against multi-bit errors. Compared to state-of-the-art, the proposed architecture provides 24% vulnerability savings when averaged across numerous experiments, while reducing the vulnerability by more than 60% for selected applications and application phases.

Original languageEnglish (US)
Title of host publication2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-10
Number of pages10
ISBN (Electronic)9781467383219
DOIs
StatePublished - Nov 17 2015
EventInternational Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015 - Amsterdam, Netherlands
Duration: Oct 4 2015Oct 9 2015

Publication series

Name2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015

Conference

ConferenceInternational Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015
Country/TerritoryNetherlands
CityAmsterdam
Period10/4/1510/9/15

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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