Abstract
The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.
Original language | English (US) |
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Pages | 240-245 |
Number of pages | 6 |
State | Published - 2001 |
Event | 19th IEEE VLSI Test Symposium - Marina del Rey, CA, United States Duration: Apr 29 2001 → May 3 2001 |
Other
Other | 19th IEEE VLSI Test Symposium |
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Country/Territory | United States |
City | Marina del Rey, CA |
Period | 4/29/01 → 5/3/01 |
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering