RT-level fault simulation based on symbolic propagation

O. Sinanoglu; A. Orailoglu

RT-level fault simulation based on symbolic propagation

Research output: Contribution to conference › Paper › peer-review

Abstract

The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.

Original language	English (US)
Pages	240-245
Number of pages	6
State	Published - 2001
Event	19th IEEE VLSI Test Symposium - Marina del Rey, CA, United States Duration: Apr 29 2001 → May 3 2001

Other

Other	19th IEEE VLSI Test Symposium
Country/Territory	United States
City	Marina del Rey, CA
Period	4/29/01 → 5/3/01

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

Cite this

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title = "RT-level fault simulation based on symbolic propagation",

abstract = "The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.",

author = "O. Sinanoglu and A. Orailoglu",

year = "2001",

language = "English (US)",

pages = "240--245",

note = "19th IEEE VLSI Test Symposium ; Conference date: 29-04-2001 Through 03-05-2001",

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TY - CONF

T1 - RT-level fault simulation based on symbolic propagation

AU - Sinanoglu, O.

AU - Orailoglu, A.

PY - 2001

Y1 - 2001

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AB - The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.

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M3 - Paper

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T2 - 19th IEEE VLSI Test Symposium

Y2 - 29 April 2001 through 3 May 2001

ER -

RT-level fault simulation based on symbolic propagation

Abstract

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ASJC Scopus subject areas

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