TY - GEN
T1 - Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures
AU - Diniz, Claudio Machado
AU - Shafique, Muhammad
AU - Bampi, Sergio
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2014 Technical University of Munich (TUM).
Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014/10/16
Y1 - 2014/10/16
N2 - Run-time mixed-grained reconfigurable architectures emerged as an efficient solution to deal with the heterogeneous and at-design-time unpredictable nature of advanced applications. Due to interconnection limitations, the reconfigurable elements are grouped into tiles communicating through an on-chip network. State-of-the-art run-time accelerator binding schemes, i.e., mapping the accelerators to elements in the physical reconfigurable array, do not deal with such tile-based architectures. We propose a new scheme for run-time accelerator binding into our tile-based mixed-grained reconfigurable architecture. By means of an advanced video encoding application, we illustrate that our scheme reduces the inter-tile communication overhead by up to 44% (avg. 23%).
AB - Run-time mixed-grained reconfigurable architectures emerged as an efficient solution to deal with the heterogeneous and at-design-time unpredictable nature of advanced applications. Due to interconnection limitations, the reconfigurable elements are grouped into tiles communicating through an on-chip network. State-of-the-art run-time accelerator binding schemes, i.e., mapping the accelerators to elements in the physical reconfigurable array, do not deal with such tile-based architectures. We propose a new scheme for run-time accelerator binding into our tile-based mixed-grained reconfigurable architecture. By means of an advanced video encoding application, we illustrate that our scheme reduces the inter-tile communication overhead by up to 44% (avg. 23%).
KW - Binding
KW - Reconfigurable architecture
KW - Tiles
UR - http://www.scopus.com/inward/record.url?scp=84911165172&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84911165172&partnerID=8YFLogxK
U2 - 10.1109/FPL.2014.6927392
DO - 10.1109/FPL.2014.6927392
M3 - Conference contribution
AN - SCOPUS:84911165172
T3 - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
Y2 - 1 September 2014 through 5 September 2014
ER -