Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures

Claudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jorg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Run-time mixed-grained reconfigurable architectures emerged as an efficient solution to deal with the heterogeneous and at-design-time unpredictable nature of advanced applications. Due to interconnection limitations, the reconfigurable elements are grouped into tiles communicating through an on-chip network. State-of-the-art run-time accelerator binding schemes, i.e., mapping the accelerators to elements in the physical reconfigurable array, do not deal with such tile-based architectures. We propose a new scheme for run-time accelerator binding into our tile-based mixed-grained reconfigurable architecture. By means of an advanced video encoding application, we illustrate that our scheme reduces the inter-tile communication overhead by up to 44% (avg. 23%).

Original languageEnglish (US)
Title of host publicationConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9783000446450
DOIs
StatePublished - Oct 16 2014
Event24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany
Duration: Sep 1 2014Sep 5 2014

Publication series

NameConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Conference

Conference24th International Conference on Field Programmable Logic and Applications, FPL 2014
CountryGermany
CityMunich
Period9/1/149/5/14

Keywords

  • Binding
  • Reconfigurable architecture
  • Tiles

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

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