TY - GEN
T1 - Run-time instruction set selection in a transmutable embedded processor
AU - Bauer, Lars
AU - Shafique, Muhammad
AU - Henkel, Jörg
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2008
Y1 - 2008
N2 - We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run-time. In those scenarios, current (extensible) embedded processors are less efficient since they are not run-time adaptive. We have identified the instruction set selection to be a critical step to perform at run time and hence we focus this paper on that crucial part. Our paradigm conducts as many steps as possible at compile/design time and as little as necessary at run time with the constraint to provide a sufficient flexibility to react to non-predictive application behavior efficiently. We provide an in-depth analysis of our scheme and achieve a speed-up of up to 7.19× (average: 3.63×) compared to state-of-the-art adaptive approaches (like 19). As an application, we have employed a whole H.264 video encoder though our scheme is by principle applicable to many other embedded applications. Our results are evaluated by an implementation of the instruction set selection for our transmutable processor on an FPGA platform.
AB - We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run-time. In those scenarios, current (extensible) embedded processors are less efficient since they are not run-time adaptive. We have identified the instruction set selection to be a critical step to perform at run time and hence we focus this paper on that crucial part. Our paradigm conducts as many steps as possible at compile/design time and as little as necessary at run time with the constraint to provide a sufficient flexibility to react to non-predictive application behavior efficiently. We provide an in-depth analysis of our scheme and achieve a speed-up of up to 7.19× (average: 3.63×) compared to state-of-the-art adaptive approaches (like 19). As an application, we have employed a whole H.264 video encoder though our scheme is by principle applicable to many other embedded applications. Our results are evaluated by an implementation of the instruction set selection for our transmutable processor on an FPGA platform.
KW - ASIP
KW - Extensible embedded processors
KW - Reconfigurable computing
KW - Run-time adaptation
KW - Special instruction
UR - http://www.scopus.com/inward/record.url?scp=51549087415&partnerID=8YFLogxK
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U2 - 10.1109/DAC.2008.4555781
DO - 10.1109/DAC.2008.4555781
M3 - Conference contribution
AN - SCOPUS:51549087415
SN - 9781605581156
T3 - Proceedings - Design Automation Conference
SP - 56
EP - 61
BT - Proceedings of the 45th Design Automation Conference, DAC
T2 - 45th Design Automation Conference, DAC
Y2 - 8 June 2008 through 13 June 2008
ER -