SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks

Maria I. Mera Collantes, Zahra Ghodsi, Siddharth Garg

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We present Safe-TPU, a framework for secure computations of Deep Neural Networks (DNNs) in untrusted hardware corrupted by Trojans or fault injection attacks. This work leverages previous advances on interactive proof (IP) systems for verifying, at run-time, the correctness of a neural network's computations, and makes three new contributions: (1) We present a Trojan resilient DNN hardware accelerator based on interactive proofs; (2) We introduce new protocol enhancements that significantly reduce the space and time required to generate proofs; and (3) we propose an implementation of Safe-TPU with high parallelism and reuse of existing resources already deployed in the baseline DNN accelerator. We prototype Safe-TPU on an FPGA and analyze its security guarantees. Experimentally, we show that Safe-TPU's area overhead is small (28%) over the baseline DNN accelerator and is 3.15× faster than state-of-the-art, while at the same time, Safe-TPU guarantees to catch, with high probability, any incorrect computations.

Original languageEnglish (US)
Title of host publicationProceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
PublisherIEEE Computer Society
ISBN (Electronic)9781728153599
StatePublished - Apr 2020
Event38th IEEE VLSI Test Symposium, VTS 2020 - San Diego, United States
Duration: Apr 5 2020Apr 8 2020

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference38th IEEE VLSI Test Symposium, VTS 2020
Country/TerritoryUnited States
CitySan Diego

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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