TY - GEN
T1 - SafeTPU
T2 - 38th IEEE VLSI Test Symposium, VTS 2020
AU - Mera Collantes, Maria I.
AU - Ghodsi, Zahra
AU - Garg, Siddharth
N1 - Funding Information:
This work was funded in part by NSF Award #1553419 and #1646671.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/4
Y1 - 2020/4
N2 - We present Safe-TPU, a framework for secure computations of Deep Neural Networks (DNNs) in untrusted hardware corrupted by Trojans or fault injection attacks. This work leverages previous advances on interactive proof (IP) systems for verifying, at run-time, the correctness of a neural network's computations, and makes three new contributions: (1) We present a Trojan resilient DNN hardware accelerator based on interactive proofs; (2) We introduce new protocol enhancements that significantly reduce the space and time required to generate proofs; and (3) we propose an implementation of Safe-TPU with high parallelism and reuse of existing resources already deployed in the baseline DNN accelerator. We prototype Safe-TPU on an FPGA and analyze its security guarantees. Experimentally, we show that Safe-TPU's area overhead is small (28%) over the baseline DNN accelerator and is 3.15× faster than state-of-the-art, while at the same time, Safe-TPU guarantees to catch, with high probability, any incorrect computations.
AB - We present Safe-TPU, a framework for secure computations of Deep Neural Networks (DNNs) in untrusted hardware corrupted by Trojans or fault injection attacks. This work leverages previous advances on interactive proof (IP) systems for verifying, at run-time, the correctness of a neural network's computations, and makes three new contributions: (1) We present a Trojan resilient DNN hardware accelerator based on interactive proofs; (2) We introduce new protocol enhancements that significantly reduce the space and time required to generate proofs; and (3) we propose an implementation of Safe-TPU with high parallelism and reuse of existing resources already deployed in the baseline DNN accelerator. We prototype Safe-TPU on an FPGA and analyze its security guarantees. Experimentally, we show that Safe-TPU's area overhead is small (28%) over the baseline DNN accelerator and is 3.15× faster than state-of-the-art, while at the same time, Safe-TPU guarantees to catch, with high probability, any incorrect computations.
UR - http://www.scopus.com/inward/record.url?scp=85086500279&partnerID=8YFLogxK
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U2 - 10.1109/VTS48691.2020.9107564
DO - 10.1109/VTS48691.2020.9107564
M3 - Conference contribution
AN - SCOPUS:85086500279
T3 - Proceedings of the IEEE VLSI Test Symposium
BT - Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
PB - IEEE Computer Society
Y2 - 5 April 2020 through 8 April 2020
ER -