SARLock: SAT attack resistant logic locking

Muhammad Yasin; Bodhisatwa Mazumdar; Jeyavijayan J.V. Rajendran; Ozgur Sinanoglu

doi:10.1109/HST.2016.7495588

SARLock: SAT attack resistant logic locking

Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan J.V. Rajendran, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy, hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken multiple attempts in breaking logic locking techniques and recovering its secret key. A Boolean Satisfiability (SAT) based attack has been recently presented that breaks all the existing combinational logic locking techniques. In this paper, we develop a lightweight countermeasure against this and other attacks that aim at gradually pruning the key search space. Our proposed logic locking technique, referred to as SARLock, maximizes the required number of distinguishing input patterns to recover the secret key. SARLock thwarts the SAT attack by rendering the attack effort exponential in the number of bits in the secret key, while its overhead grows only linearly.

Original language	English (US)
Title of host publication	Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	236-241
Number of pages	6
ISBN (Electronic)	9781467388252
DOIs	https://doi.org/10.1109/HST.2016.7495588
State	Published - Jun 20 2016
Event	2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016 - McLean, United States Duration: May 3 2016 → May 5 2016

Publication series

Name	Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016

Other

Other	2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016
Country/Territory	United States
City	McLean
Period	5/3/16 → 5/5/16

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

10.1109/HST.2016.7495588

Cite this

Yasin, M., Mazumdar, B., Rajendran, J. J. V., & Sinanoglu, O. (2016). SARLock: SAT attack resistant logic locking. In Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016 (pp. 236-241). Article 7495588 (Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HST.2016.7495588

SARLock: SAT attack resistant logic locking. / Yasin, Muhammad; Mazumdar, Bodhisatwa; Rajendran, Jeyavijayan J.V. et al.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 236-241 7495588 (Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yasin, M, Mazumdar, B, Rajendran, JJV & Sinanoglu, O 2016, SARLock: SAT attack resistant logic locking. in Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016., 7495588, Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, Institute of Electrical and Electronics Engineers Inc., pp. 236-241, 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, McLean, United States, 5/3/16. https://doi.org/10.1109/HST.2016.7495588

Yasin M, Mazumdar B, Rajendran JJV, Sinanoglu O. SARLock: SAT attack resistant logic locking. In Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 236-241. 7495588. (Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016). doi: 10.1109/HST.2016.7495588

Yasin, Muhammad ; Mazumdar, Bodhisatwa ; Rajendran, Jeyavijayan J.V. et al. / SARLock : SAT attack resistant logic locking. Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 236-241 (Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016).

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abstract = "Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy, hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken multiple attempts in breaking logic locking techniques and recovering its secret key. A Boolean Satisfiability (SAT) based attack has been recently presented that breaks all the existing combinational logic locking techniques. In this paper, we develop a lightweight countermeasure against this and other attacks that aim at gradually pruning the key search space. Our proposed logic locking technique, referred to as SARLock, maximizes the required number of distinguishing input patterns to recover the secret key. SARLock thwarts the SAT attack by rendering the attack effort exponential in the number of bits in the secret key, while its overhead grows only linearly.",

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SARLock: SAT attack resistant logic locking

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