SARLock: SAT attack resistant logic locking

Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan J.V. Rajendran, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy, hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken multiple attempts in breaking logic locking techniques and recovering its secret key. A Boolean Satisfiability (SAT) based attack has been recently presented that breaks all the existing combinational logic locking techniques. In this paper, we develop a lightweight countermeasure against this and other attacks that aim at gradually pruning the key search space. Our proposed logic locking technique, referred to as SARLock, maximizes the required number of distinguishing input patterns to recover the secret key. SARLock thwarts the SAT attack by rendering the attack effort exponential in the number of bits in the secret key, while its overhead grows only linearly.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages236-241
Number of pages6
ISBN (Electronic)9781467388252
DOIs
StatePublished - Jun 20 2016
Event2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016 - McLean, United States
Duration: May 3 2016May 5 2016

Publication series

NameProceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016

Other

Other2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016
CountryUnited States
CityMcLean
Period5/3/165/5/16

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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