TY - GEN
T1 - Scan attack in presence of mode-reset countermeasure
AU - Ali, Sk Subidh
AU - Saeed, Samah Mohamed
AU - Sinanoglu, Ozgur
AU - Karri, Ramesh
PY - 2013
Y1 - 2013
N2 - Design for testability (DFT) is the most common testing technique used in the modern VLSI industries. However, when this technique is incorporated in a cryptographic circuit, it may open a back door to an attacker. The attacker can get access to the internal scan chains by switching the device from the normal mode to the test mode and then observe the chip content. The scan cells which were originally used to enhance the testability, can thus be misused to access the intermediate results of the cryptographic algorithm running inside the chip. One countermeasure against such attacks is to reset the device whenever there is a switch from the normal mode to the test mode. In this work we are going to analyse this countermeasure and show that it is not completely secure against scan attack. We show that an attack is possible using only the test mode which will bypass the countermeasure.
AB - Design for testability (DFT) is the most common testing technique used in the modern VLSI industries. However, when this technique is incorporated in a cryptographic circuit, it may open a back door to an attacker. The attacker can get access to the internal scan chains by switching the device from the normal mode to the test mode and then observe the chip content. The scan cells which were originally used to enhance the testability, can thus be misused to access the intermediate results of the cryptographic algorithm running inside the chip. One countermeasure against such attacks is to reset the device whenever there is a switch from the normal mode to the test mode. In this work we are going to analyse this countermeasure and show that it is not completely secure against scan attack. We show that an attack is possible using only the test mode which will bypass the countermeasure.
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U2 - 10.1109/IOLTS.2013.6604086
DO - 10.1109/IOLTS.2013.6604086
M3 - Conference contribution
AN - SCOPUS:84885235108
SN - 9781479906628
T3 - Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013
SP - 230
EP - 231
BT - Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013
T2 - 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013
Y2 - 8 July 2013 through 10 July 2013
ER -