Scan cell positioning for boosting the compression of fan-out networks

Ozgur Sinanoglu, Mohammed Al-Mulla, Noora A. Shunaiber, Alex Orailoglu

Research output: Contribution to journalArticlepeer-review

Abstract

Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.

Original languageEnglish (US)
Pages (from-to)939-948
Number of pages10
JournalJournal of Computer Science and Technology
Volume24
Issue number5
DOIs
StatePublished - Sep 2009

Keywords

  • Scan architecture design
  • Scan cell reordering
  • Scan-based testing
  • Test data compression

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

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