Scan design: Basics, advancements, and vulnerabilities

Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingChapter


The increasing design complexity of modern Integrated Chips (IC) has reflected into exacerbated challenges in manufacturing testing. In this respect, scan is the most widely used design for testability (DfT) technique that overcomes the manufacturing test challenges by enhancing the access and thus, testability. However, scan can also open a back door to an attacker when implemented in security critical chips. Although some applications disable access to the scan chains upon manufacturing test, other applications require this access to enable in-field testing and debugging capabilities. This chapter aims at providing testable yet secure scan-based DfT techniques. We first describe various cost-effective DfT techniques to overcome the test challenges, such as low controllability and observability, which in turn leads to high test cost and low test quality. In particular, we review the challenges and opportunities in widely utilized compression-based scan design. We then highlight the security vulnerabilities of basic scan as well as these advanced DfT techniques. We describe multiple scan attacks that misuse representative test infrastructures. A detailed analysis is also performed to figure out the fundamental limitations of these attacks.

Original languageEnglish (US)
Title of host publicationHardware Security and Trust
Subtitle of host publicationDesign and Deployment of Integrated Circuits in a Threatened Environment
PublisherSpringer International Publishing
Number of pages20
ISBN (Electronic)9783319443188
ISBN (Print)9783319443164
StatePublished - Jan 1 2017


  • AES
  • Compactor
  • Decompressor
  • DfT
  • Scan attack
  • Scan chain
  • Security
  • Test-mode-only attack
  • Testability

ASJC Scopus subject areas

  • General Engineering
  • General Computer Science


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