TY - GEN
T1 - SeBoost
T2 - International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015
AU - Pagani, Santiago
AU - Shafique, Muhammad
AU - Khdr, Heba
AU - Chen, Jian Jia
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2015 IEEE.
Copyright:
Copyright 2016 Elsevier B.V., All rights reserved.
PY - 2015/11/17
Y1 - 2015/11/17
N2 - Boosting techniques have been widely adopted in commercial multicore and manycore systems, mainly because they provide means to satisfy performance requirements surges, for one or more cores, at run-time. Current boosting techniques select the boosting levels (for boosted cores) and the throttle-down levels (for non-boosted cores) either arbitrarily or through step-wise control approaches. These methods might result in unnecessary performance losses for the non-boosted cores, in short boosting intervals, in failing to satisfy the required performance surges, or in unnecessary high power and energy consumption. This paper presents an efficient and lightweight run-time boosting technique based on transient temperature estimation, called seBoost. Our technique guarantees meeting the performance requirements surges at run-time, thus maximizing the boosting time with a minimum loss of performance for the non-boosted cores.
AB - Boosting techniques have been widely adopted in commercial multicore and manycore systems, mainly because they provide means to satisfy performance requirements surges, for one or more cores, at run-time. Current boosting techniques select the boosting levels (for boosted cores) and the throttle-down levels (for non-boosted cores) either arbitrarily or through step-wise control approaches. These methods might result in unnecessary performance losses for the non-boosted cores, in short boosting intervals, in failing to satisfy the required performance surges, or in unnecessary high power and energy consumption. This paper presents an efficient and lightweight run-time boosting technique based on transient temperature estimation, called seBoost. Our technique guarantees meeting the performance requirements surges at run-time, thus maximizing the boosting time with a minimum loss of performance for the non-boosted cores.
UR - http://www.scopus.com/inward/record.url?scp=84963723547&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84963723547&partnerID=8YFLogxK
U2 - 10.1109/CODESISSS.2015.7331373
DO - 10.1109/CODESISSS.2015.7331373
M3 - Conference contribution
AN - SCOPUS:84963723547
T3 - 2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015
SP - 104
EP - 113
BT - 2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 4 October 2015 through 9 October 2015
ER -