TY - JOUR
T1 - Securing Hardware Accelerators
T2 - A New Challenge for High-Level Synthesis
AU - Pilato, Christian
AU - Garg, Siddharth
AU - Wu, Kaijie
AU - Karri, Ramesh
AU - Regazzoni, Francesco
N1 - Funding Information:
Manuscript received May 24, 2017; revised October 10, 2017; accepted November 3, 2017. Date of publication November 16, 2017; date of current version September 7, 2018. This work was supported in part by the EU Commission’s H2020 Programme (CERBERO Project) under Grant 732105, and in part by the National Science Foundation under Grant A#: 1526405. The work of R. Karri was supported in part by CCS-AD, in part by NYU-AD, and in part by Boeing. The work of S. Garg was supported by Boeing. This manuscript was recommended for publication by C. Gebotys. (Corresponding author: Christian Pilato.) C. Pilato and F. Regazzoni are with the Faculty of Informatics, Advanced Learning and Research Institute, Università della Svizzera italiana, 6904 Lugano, Switzerland (e-mail: christian.pilato@usi.ch).
PY - 2018/9
Y1 - 2018/9
N2 - High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized system-on-chip architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This letter discusses extensions to HLS tools for creating secure heterogeneous architectures.
AB - High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized system-on-chip architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This letter discusses extensions to HLS tools for creating secure heterogeneous architectures.
KW - Hardware security
KW - high-level synthesis (HLS)
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U2 - 10.1109/LES.2017.2774800
DO - 10.1109/LES.2017.2774800
M3 - Article
AN - SCOPUS:85035145064
VL - 10
SP - 77
EP - 80
JO - IEEE Embedded Systems Letters
JF - IEEE Embedded Systems Letters
SN - 1943-0663
IS - 3
M1 - 8114281
ER -