Securing Hardware Accelerators: A New Challenge for High-Level Synthesis

Christian Pilato, Siddharth Garg, Kaijie Wu, Ramesh Karri, Francesco Regazzoni

Research output: Contribution to journalArticle

Abstract

High-level synthesis (HLS) tools have made significant progress in the past few years, improving the design productivity for hardware accelerators and becoming mainstream in industry to create specialized system-on-chip architectures. Increasing the level of security of these heterogeneous architectures is becoming critical. However, state-of-the-art security countermeasures are still applied only to the code executing on the processor cores or manually implemented into the generated components, leading to suboptimal and sometimes even insecure designs. This letter discusses extensions to HLS tools for creating secure heterogeneous architectures.

Original languageEnglish (US)
Article number8114281
Pages (from-to)77-80
Number of pages4
JournalIEEE Embedded Systems Letters
Volume10
Issue number3
DOIs
StatePublished - Sep 2018

Keywords

  • Hardware security
  • high-level synthesis (HLS)

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)

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