Securing processors against insider attacks: A circuit-microarchitecture co-design approach

Jeyavijayan Rajendran, Arun Karthik Kanuparthi, Ramesh Karri, Mohamed Zahran, Sateesh K. Addepalli, Gaston Ormazabal

Research output: Contribution to journalArticlepeer-review

Abstract

A joint circuit-architecture-level design approach is proposed that helps in preventing or detecting Trojan attacks. The performance impact of processor encryption depends on how often the security module is used. If a security module checks the instructions often, then processor encryption will have a high performance impact. The key size used for encryption increases as the detection sensitivity of detection technique increases. Apart from design size, power consumption and path-delays can also be used as metrics for detection sensitivity of a detection technique. Encrypting the entire pipeline will significantly impact processor's performance. Hence, we encrypt only some of the pipeline units depending up on the security modules in the processor. The TrustNet and DataWatch security modules are distributed, and hence multiple units are encrypted.

Original languageEnglish (US)
Article number6472275
Pages (from-to)35-44
Number of pages10
JournalIEEE Design and Test
Volume30
Issue number2
DOIs
StatePublished - 2013

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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