Security analysis of Anti-SAT

Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran

doi:10.1109/ASPDAC.2017.7858346

Security analysis of Anti-SAT

Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Logic encryption protects integrated circuits (ICs) against intellectual property (IP) piracy and overbuilding attacks by encrypting the IC with a key. A Boolean satisfiability (SAT) based attack breaks all existing logic encryption technique within few hours. Recently, a defense mechanism known as Anti-SAT was presented that protects against SAT attack, by rendering the SAT-attack effort exponential in terms of the number of key gates. In this paper, we highlight the vulnerabilities of Anti-SAT and propose signal probability skew (SPS) attack against Anti-SAT block. SPS attack leverages the structural traces in Anti-SAT block to identify and isolate Anti-SAT block. The attack is 100% successful on all variants of Anti-SAT block. SPS attack is scalable to large circuits, as it breaks circuits with up to 22K gates within two minutes.

Original language	English (US)
Title of host publication	2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	342-347
Number of pages	6
ISBN (Electronic)	9781509015580
DOIs	https://doi.org/10.1109/ASPDAC.2017.7858346
State	Published - Feb 16 2017
Event	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan Duration: Jan 16 2017 → Jan 19 2017

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Country/Territory	Japan
City	Chiba
Period	1/16/17 → 1/19/17

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ASPDAC.2017.7858346

Cite this

Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J. (2017). Security analysis of Anti-SAT. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 (pp. 342-347). Article 7858346 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2017.7858346

Security analysis of Anti-SAT. / Yasin, Muhammad; Mazumdar, Bodhisatwa; Sinanoglu, Ozgur et al.
2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 342-347 7858346 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yasin, M, Mazumdar, B, Sinanoglu, O & Rajendran, J 2017, Security analysis of Anti-SAT. in 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017., 7858346, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 342-347, 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, 1/16/17. https://doi.org/10.1109/ASPDAC.2017.7858346

@inproceedings{2460af99b2fc483d92fe17d518aae753,

title = "Security analysis of Anti-SAT",

abstract = "Logic encryption protects integrated circuits (ICs) against intellectual property (IP) piracy and overbuilding attacks by encrypting the IC with a key. A Boolean satisfiability (SAT) based attack breaks all existing logic encryption technique within few hours. Recently, a defense mechanism known as Anti-SAT was presented that protects against SAT attack, by rendering the SAT-attack effort exponential in terms of the number of key gates. In this paper, we highlight the vulnerabilities of Anti-SAT and propose signal probability skew (SPS) attack against Anti-SAT block. SPS attack leverages the structural traces in Anti-SAT block to identify and isolate Anti-SAT block. The attack is 100% successful on all variants of Anti-SAT block. SPS attack is scalable to large circuits, as it breaks circuits with up to 22K gates within two minutes.",

author = "Muhammad Yasin and Bodhisatwa Mazumdar and Ozgur Sinanoglu and Jeyavijayan Rajendran",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 ; Conference date: 16-01-2017 Through 19-01-2017",

year = "2017",

month = feb,

day = "16",

doi = "10.1109/ASPDAC.2017.7858346",

language = "English (US)",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "342--347",

booktitle = "2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017",

}

TY - GEN

T1 - Security analysis of Anti-SAT

AU - Yasin, Muhammad

AU - Mazumdar, Bodhisatwa

AU - Sinanoglu, Ozgur

AU - Rajendran, Jeyavijayan

PY - 2017/2/16

Y1 - 2017/2/16

N2 - Logic encryption protects integrated circuits (ICs) against intellectual property (IP) piracy and overbuilding attacks by encrypting the IC with a key. A Boolean satisfiability (SAT) based attack breaks all existing logic encryption technique within few hours. Recently, a defense mechanism known as Anti-SAT was presented that protects against SAT attack, by rendering the SAT-attack effort exponential in terms of the number of key gates. In this paper, we highlight the vulnerabilities of Anti-SAT and propose signal probability skew (SPS) attack against Anti-SAT block. SPS attack leverages the structural traces in Anti-SAT block to identify and isolate Anti-SAT block. The attack is 100% successful on all variants of Anti-SAT block. SPS attack is scalable to large circuits, as it breaks circuits with up to 22K gates within two minutes.

AB - Logic encryption protects integrated circuits (ICs) against intellectual property (IP) piracy and overbuilding attacks by encrypting the IC with a key. A Boolean satisfiability (SAT) based attack breaks all existing logic encryption technique within few hours. Recently, a defense mechanism known as Anti-SAT was presented that protects against SAT attack, by rendering the SAT-attack effort exponential in terms of the number of key gates. In this paper, we highlight the vulnerabilities of Anti-SAT and propose signal probability skew (SPS) attack against Anti-SAT block. SPS attack leverages the structural traces in Anti-SAT block to identify and isolate Anti-SAT block. The attack is 100% successful on all variants of Anti-SAT block. SPS attack is scalable to large circuits, as it breaks circuits with up to 22K gates within two minutes.

UR - http://www.scopus.com/inward/record.url?scp=85015301539&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85015301539&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2017.7858346

DO - 10.1109/ASPDAC.2017.7858346

M3 - Conference contribution

AN - SCOPUS:85015301539

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 342

EP - 347

BT - 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017

Y2 - 16 January 2017 through 19 January 2017

ER -

Security analysis of Anti-SAT

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