Security analysis of logic obfuscation

Jeyavijayan Rajendran; Youngok Pino; Ozgur Sinanoglu; Ramesh Karri

doi:10.1145/2228360.2228377

Security analysis of logic obfuscation

Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Due to globalization of Integrated Circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware trojans. EPIC [1] obfuscates the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the obfuscated netlist, in a time linear to the number of keys, by sensitizing the key values to the output. We then develop techniques to fix this vulnerability and make obfuscation truly exponential in the number of inserted keys.

Original language	English (US)
Title of host publication	Proceedings of the 49th Annual Design Automation Conference, DAC '12
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	83-89
Number of pages	7
ISBN (Print)	9781450311991
DOIs	https://doi.org/10.1145/2228360.2228377
State	Published - 2012
Event	49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States Duration: Jun 3 2012 → Jun 7 2012

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Other

Other	49th Annual Design Automation Conference, DAC '12
Country/Territory	United States
City	San Francisco, CA
Period	6/3/12 → 6/7/12

Keywords

IP protection
logic obfuscation

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Access to Document

10.1145/2228360.2228377

Cite this

Security analysis of logic obfuscation. / Rajendran, Jeyavijayan; Pino, Youngok; Sinanoglu, Ozgur et al.
Proceedings of the 49th Annual Design Automation Conference, DAC '12. Institute of Electrical and Electronics Engineers Inc., 2012. p. 83-89 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rajendran, J, Pino, Y, Sinanoglu, O & Karri, R 2012, Security analysis of logic obfuscation. in Proceedings of the 49th Annual Design Automation Conference, DAC '12. Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 83-89, 49th Annual Design Automation Conference, DAC '12, San Francisco, CA, United States, 6/3/12. https://doi.org/10.1145/2228360.2228377

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abstract = "Due to globalization of Integrated Circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware trojans. EPIC [1] obfuscates the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the obfuscated netlist, in a time linear to the number of keys, by sensitizing the key values to the output. We then develop techniques to fix this vulnerability and make obfuscation truly exponential in the number of inserted keys.",

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author = "Jeyavijayan Rajendran and Youngok Pino and Ozgur Sinanoglu and Ramesh Karri",

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AB - Due to globalization of Integrated Circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware trojans. EPIC [1] obfuscates the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the obfuscated netlist, in a time linear to the number of keys, by sensitizing the key values to the output. We then develop techniques to fix this vulnerability and make obfuscation truly exponential in the number of inserted keys.

KW - IP protection

KW - logic obfuscation

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Security analysis of logic obfuscation

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

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