TY - GEN
T1 - Security assessment of microfluidic fully-programmable-valve-array biochips
AU - Shayan, Mohammed
AU - Bhattacharjee, Sukanta
AU - Song, Yong Ak
AU - Chakrabarty, Krishnendu
AU - Karri, Ramesh
N1 - Funding Information:
ACKNOWLEDGMENT This research is supported in part by the Army Research Office under grant number W911NF-17-1-0320, NSF Award numbers CNS-1833622 and CNS-1833624, NYU Center for Cyber Security (CCS), and CCS-AD.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/5/9
Y1 - 2019/5/9
N2 - The fully-programmable-valve-array (FPVA) is a general-purpose programmable flow-based microfluidic platform, akin to the VLSI field-programmable gate array (FPGA). FPVAs are dynamically reconfigurable and hence are suitable in a broad spectrum of applications involving immunoassays and cell analysis. Since these applications are safety-critical, addressing security concerns is vital for the success and adoption of FPVAs. This study evaluates the security of FPVA biochips. We show that FPVAs are vulnerable to malicious operations similar to digital and flow-based microfluidic biochips. FPVAs are further prone to new classes of attacks - tunneling and deliberate aging. The study establishes security metrics and describes possible attacks on real-life bioassays.
AB - The fully-programmable-valve-array (FPVA) is a general-purpose programmable flow-based microfluidic platform, akin to the VLSI field-programmable gate array (FPGA). FPVAs are dynamically reconfigurable and hence are suitable in a broad spectrum of applications involving immunoassays and cell analysis. Since these applications are safety-critical, addressing security concerns is vital for the success and adoption of FPVAs. This study evaluates the security of FPVA biochips. We show that FPVAs are vulnerable to malicious operations similar to digital and flow-based microfluidic biochips. FPVAs are further prone to new classes of attacks - tunneling and deliberate aging. The study establishes security metrics and describes possible attacks on real-life bioassays.
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U2 - 10.1109/VLSID.2019.00053
DO - 10.1109/VLSID.2019.00053
M3 - Conference contribution
AN - SCOPUS:85066805268
T3 - Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019
SP - 197
EP - 202
BT - Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd International Conference on VLSI Design, VLSID 2019
Y2 - 5 January 2019 through 9 January 2019
ER -