Silicon-proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption

Mohammed Nabeel, Homer Gamil, Deepraj Soni, Mohammed Ashraf, Mizan Abraha Gebremichael, Eduardo Chielle, Ramesh Karri, Mihai Sanduleanu, Michail Maniatakos

Research output: Contribution to journalArticlepeer-review

Abstract

In this work, we elaborate on our endeavors to design, implement, fabricate, and post-silicon validate CoFHEE 1, a co-processor for low-level polynomial operations targeting Fully Homomorphic Encryption execution. With a compact design area of 12mm2, CoFHEE features ASIC implementations of fundamental polynomial operations, including polynomial addition and subtraction, Hadamard product, and Number Theoretic Transform, which underlie most higher-level FHE primitives. CoFHEE is capable of natively supporting polynomial degrees of up to n = 214 with a coefficient size of 128 bits, and has been fabricated and silicon-verified using 55nm CMOS technology. To evaluate it, we conduct performance and power experiments on our chip, and compare it to state-of-the-art software implementations and other ASIC designs.

Original languageEnglish (US)
Pages (from-to)1
Number of pages1
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOIs
StateAccepted/In press - 2024

Keywords

  • ASIC
  • Co-processor
  • Computer architecture
  • Data privacy
  • Design automation
  • Encrypted computation
  • Fully Homomorphic Encryption
  • Homomorphic encryption
  • Integrated circuits
  • Phase locked loops
  • Standards
  • Transforms

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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