TY - JOUR
T1 - SIMCom
T2 - Statistical sniffing of inter-module communications for runtime hardware trojan detection
AU - Khalid, Faiq
AU - Hasan, Syed Rafay
AU - Hasan, Osman
AU - Shafique, Muhammad
N1 - Funding Information:
Syed Rafay Hasan received the B.Eng. degree in electrical engineering from the NED University of Engineering and Technology, Pakistan, and the M.Eng. and Ph.D. degrees in electrical engineering from Concordia University, Montreal, QC, Canada. From 2006 to 2009, he was an Adjunct Faculty Member with Concordia University. From 2009 to 2011, he was a Research Associate with the Ecole Polytechnique de Montreal. Since 2011, he has been with the Electrical and Computer Engineering Department, Tennessee Tech University, Cookeville, TN, USA, where he is currently an Associate Professor. He has published more than 67 peer-reviewed journal and conference papers. His current research interests include hardware design security in the Internet of Things (IoT), hardware implementation of deep learning, deployment of convolution neural networks in the IoT edge devices, and hardware security issues due to adversarial learning. He is a Full Member of Sigma Xi and a Life Member of the Pakistan Engineering Council. He received the Postdoctoral Fellowship Award from the Scholarship Regroupment Stratgique en Microsystmes du Québec, in 2011, the Faculty Research Award from Tennessee Tech University, from 2013 to 2014 and from 2015 to 2016, the Kinslow Outstanding Research Paper Award from the College of Engineering, Tennessee Tech University, in 2015, and the Summer Faculty Fellowship Award from the Air force Research Lab (AFRL). He was a recipient of the Sigma Xi Outstanding Research Award, in 2012. He has received research and teaching funding from NSF, ICT-funds UAE, AFRL, and Intel Inc. He has been part of the funded research projects, as a PI or a Co-PI, that worth more than $1.1 million. He is the Session Chair and a Technical Program Committee Member of several IEEE conferences including ISCAS, ICCD, MWSCAS, and NEWCAS, and a Regular Reviewer for several IEEE TRANSACTIONS and other journals including TCAS-II, IEEE ACCESS, Integration, the VLSI Journal, IET Circuit Devices and Systems, and IEEE EMBEDDED SYSTEMS LETTERS.
Funding Information:
This work is supported in parts by the Austrian Research Promotion Agency (FFG) and the Austrian Federal Ministry for Transport, Innovation, and Technology (BMVIT) under the ICT of the Future project, IoT4CPS: Trustworthy IoT for Cyber-Physical Systems.
Funding Information:
This work is supported in parts by the Austrian Research Promotion Agency (FFG) and the Austrian Federal Ministry for Transport, Innovation, and Technology (BMVIT) under the ICT of the Future project, IoT4CPS: Trustworthy IoT for Cyber-Physical Systems.
Publisher Copyright:
© 2020 Elsevier B.V.
PY - 2020/9
Y1 - 2020/9
N2 - Timely detection of Hardware Trojans (HTs) has become a major challenge for secure integrated circuits. We present a run-time methodology for HT detection that employs a multi-parameter statistical traffic modeling of the communication channel in a given System-on-Chip (SoC), named as SIMCom. The main idea is to model the communication using multiple side-channel information like the Hurst exponent, the standard deviation of the injection distribution, and the hop distribution jointly to accurately identify HT-based online anomalies (that affects the communication without affecting the protocols or control signals). At design time, our methodology employs a “property specification language” to define and embed assertions in the RTL, specifying the correct communication behavior of a given SoC. At run-time, it monitors the anomalies in the communication behavior by checking the execution patterns against these assertions. For illustration, we evaluate SIMCom for three SoCs, i.e., SoC1 (four single-core MC8051 and UART modules), SoC2 (four single-core MC8051, AES, ethernet, memctrl, BasicRSA, RS232 modules), and SoC3 (four single-core LEON3 connected with each other and AES, ethernet, memctrl, BasicRSA, RS23s modules microcontrollers). The experimental results show that with the combined analysis of multiple statistical parameters, SIMCom is able to detect all the benchmark Trojans (available on trust-hub) with less than 1% area and power overhead.
AB - Timely detection of Hardware Trojans (HTs) has become a major challenge for secure integrated circuits. We present a run-time methodology for HT detection that employs a multi-parameter statistical traffic modeling of the communication channel in a given System-on-Chip (SoC), named as SIMCom. The main idea is to model the communication using multiple side-channel information like the Hurst exponent, the standard deviation of the injection distribution, and the hop distribution jointly to accurately identify HT-based online anomalies (that affects the communication without affecting the protocols or control signals). At design time, our methodology employs a “property specification language” to define and embed assertions in the RTL, specifying the correct communication behavior of a given SoC. At run-time, it monitors the anomalies in the communication behavior by checking the execution patterns against these assertions. For illustration, we evaluate SIMCom for three SoCs, i.e., SoC1 (four single-core MC8051 and UART modules), SoC2 (four single-core MC8051, AES, ethernet, memctrl, BasicRSA, RS232 modules), and SoC3 (four single-core LEON3 connected with each other and AES, ethernet, memctrl, BasicRSA, RS23s modules microcontrollers). The experimental results show that with the combined analysis of multiple statistical parameters, SIMCom is able to detect all the benchmark Trojans (available on trust-hub) with less than 1% area and power overhead.
KW - Communication
KW - Hardware trojans
KW - Hurst exponent
KW - Internet-of-thing
KW - IoT
KW - Microcontrollers
KW - Statistical modeling
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U2 - 10.1016/j.micpro.2020.103122
DO - 10.1016/j.micpro.2020.103122
M3 - Article
AN - SCOPUS:85085271470
SN - 0141-9331
VL - 77
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
M1 - 103122
ER -