Abstract
In this paper we present DEFT, a system for synthesizing defect-tolerant layouts, that in-grains tolerance to fabrication induced defects. This is accomplished by dispersing nets with large overlaps into nonadjacent tracks. DEFT also affords trade-offs between area (measured as the number of tracks) and yield of the resulting layout. The defect-tolerant layouts synthesized by DEFT have been consistently superior to those generated by other layout synthesis systems.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| Pages | 166-169 |
| Number of pages | 4 |
| State | Published - 1994 |
| Event | Proceedings of the 4th Great Lakes Symposium on VLSI - Notre Dame, IN, USA Duration: Mar 4 1994 → Mar 5 1994 |
Other
| Other | Proceedings of the 4th Great Lakes Symposium on VLSI |
|---|---|
| City | Notre Dame, IN, USA |
| Period | 3/4/94 → 3/5/94 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering