Simulated annealing based yield enhancement of layouts

Ramesh Karri, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present DEFT, a system for synthesizing defect-tolerant layouts, that in-grains tolerance to fabrication induced defects. This is accomplished by dispersing nets with large overlaps into nonadjacent tracks. DEFT also affords trade-offs between area (measured as the number of tracks) and yield of the resulting layout. The defect-tolerant layouts synthesized by DEFT have been consistently superior to those generated by other layout synthesis systems.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
Pages166-169
Number of pages4
StatePublished - 1994
EventProceedings of the 4th Great Lakes Symposium on VLSI - Notre Dame, IN, USA
Duration: Mar 4 1994Mar 5 1994

Other

OtherProceedings of the 4th Great Lakes Symposium on VLSI
CityNotre Dame, IN, USA
Period3/4/943/5/94

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Karri, R., & Orailoglu, A. (1994). Simulated annealing based yield enhancement of layouts. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 166-169)