TY - GEN
T1 - Simulation and analysis of negative-bias temperature instability aging on power analysis attacks
AU - Guo, Xiaofei
AU - Karimi, Naghmeh
AU - Regazzoni, Francesco
AU - Jin, Chenglu
AU - Karri, Ramesh
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/6/29
Y1 - 2015/6/29
N2 - Transistor aging is an important failure mechanism in nanoscale designs and is a growing concern for the reliability of future systems. Transistor aging results in circuit performance degradation over time and the ultimate circuit failure. Among aging mechanisms, Negative-Bias Temperature Instability (NBTI) has become the leading limiting factor of circuit lifetime. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security, and in particular on power analysis attack. This paper fills the gap by evaluating the effects on power analysis attack. Our experimental results obtained using PRESENT algorithm show that CPA attacks are not significantly affected by aging, while the successful rate of template attack changes significantly.
AB - Transistor aging is an important failure mechanism in nanoscale designs and is a growing concern for the reliability of future systems. Transistor aging results in circuit performance degradation over time and the ultimate circuit failure. Among aging mechanisms, Negative-Bias Temperature Instability (NBTI) has become the leading limiting factor of circuit lifetime. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security, and in particular on power analysis attack. This paper fills the gap by evaluating the effects on power analysis attack. Our experimental results obtained using PRESENT algorithm show that CPA attacks are not significantly affected by aging, while the successful rate of template attack changes significantly.
UR - http://www.scopus.com/inward/record.url?scp=84942598127&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84942598127&partnerID=8YFLogxK
U2 - 10.1109/HST.2015.7140250
DO - 10.1109/HST.2015.7140250
M3 - Conference contribution
AN - SCOPUS:84942598127
T3 - Proceedings of the 2015 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2015
SP - 124
EP - 129
BT - Proceedings of the 2015 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2015
Y2 - 5 May 2015 through 7 May 2015
ER -