SLICED: Slide-based concurrent error detection technique for symmetric block ciphers

Jeyavijayan Rajendran, Hetal Borad, Shyam Mantravadi, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fault attacks, wherein faults are deliberately injected into cryptographic devices, can compromise their security. Moreover, in the emerging nanometer regime of VLSI, accidental faults will occur at very high rates. While straightforward hardware redundancy based concurrent error detection (CED) can detect transient and permanent faults, it entails 100% area overhead. On the other hand, time redundancy based CED can only detect transient faults with minimum area overhead but entails 100% time overhead. In this paper we present a general time redundancy based CED technique called SLICED for pipelined implementations of symmetric block cipher. SLICED SLIdes one encryption over another and compares their results for CED as a basis for protection against accidental faults and deliberate fault attacks.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Pages70-75
Number of pages6
DOIs
StatePublished - 2010
Event2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 14 2010

Publication series

NameProceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010

Other

Other2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Country/TerritoryUnited States
CityAnaheim, CA
Period6/13/106/14/10

Keywords

  • Concurrent Error Detection (CED)
  • Cryptography
  • Fault tolerance
  • Sliding
  • Symmetric block ciphers

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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