Sneak-path testing of memristor-based memories

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ∼32%.

Original languageEnglish (US)
Title of host publicationProceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013
Pages386-391
Number of pages6
DOIs
StatePublished - 2013
Event2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013 - Pune, India
Duration: Jan 5 2013Jan 10 2013

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013
Country/TerritoryIndia
CityPune
Period1/5/131/10/13

Keywords

  • Emerging memory technologies
  • Fault modeling
  • Memory testing
  • Metal-oxide memristors

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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