TY - GEN
T1 - Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores
AU - Subramaniyan, Arun
AU - Rehman, Semeen
AU - Shafique, Muhammad
AU - Kumar, Akash
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2017 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/5/11
Y1 - 2017/5/11
N2 - Mainstream multi-core processors employ large multilevel on-chip caches making them highly susceptible to soft errors. We demonstrate that designing a reliable cache hierarchy requires understanding the vulnerability interdependencies across different cache levels. This involves vulnerability analyses depending upon the parameters of different cache levels (partition size, line size, etc.) and the corresponding cache access patterns for different applications. This paper presents a novel soft error-aware cache architectural space exploration methodology and vulnerability analysis of multi-level caches considering their vulnerability interdependencies. Our technique significantly reduces exploration time while providing reliability-efficient cache configurations. We also show applicability/benefits for ECC-protected caches under multi-bit fault scenarios.
AB - Mainstream multi-core processors employ large multilevel on-chip caches making them highly susceptible to soft errors. We demonstrate that designing a reliable cache hierarchy requires understanding the vulnerability interdependencies across different cache levels. This involves vulnerability analyses depending upon the parameters of different cache levels (partition size, line size, etc.) and the corresponding cache access patterns for different applications. This paper presents a novel soft error-aware cache architectural space exploration methodology and vulnerability analysis of multi-level caches considering their vulnerability interdependencies. Our technique significantly reduces exploration time while providing reliability-efficient cache configurations. We also show applicability/benefits for ECC-protected caches under multi-bit fault scenarios.
UR - http://www.scopus.com/inward/record.url?scp=85020172883&partnerID=8YFLogxK
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U2 - 10.23919/DATE.2017.7926955
DO - 10.23919/DATE.2017.7926955
M3 - Conference contribution
AN - SCOPUS:85020172883
T3 - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
SP - 37
EP - 42
BT - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th Design, Automation and Test in Europe, DATE 2017
Y2 - 27 March 2017 through 31 March 2017
ER -