Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores

Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jorg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Mainstream multi-core processors employ large multilevel on-chip caches making them highly susceptible to soft errors. We demonstrate that designing a reliable cache hierarchy requires understanding the vulnerability interdependencies across different cache levels. This involves vulnerability analyses depending upon the parameters of different cache levels (partition size, line size, etc.) and the corresponding cache access patterns for different applications. This paper presents a novel soft error-aware cache architectural space exploration methodology and vulnerability analysis of multi-level caches considering their vulnerability interdependencies. Our technique significantly reduces exploration time while providing reliability-efficient cache configurations. We also show applicability/benefits for ECC-protected caches under multi-bit fault scenarios.

Original languageEnglish (US)
Title of host publicationProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9783981537093
StatePublished - May 11 2017
Event20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland
Duration: Mar 27 2017Mar 31 2017

Publication series

NameProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017


Other20th Design, Automation and Test in Europe, DATE 2017
CitySwisstech, Lausanne

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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