TY - GEN
T1 - Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing
AU - Khan, Muhammad Usman Karim
AU - Shafique, Muhammad
AU - Henkel, Jörg
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014
Y1 - 2014
N2 - The High Efficiency Video Coding (HEVC) standard aims at providing ∼50% better compression compared to its predecessor (H.264) at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this work, we present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions (i.e. so-called video tiles) which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced (through dynamically scaling the operating frequency) under a given frame-rate constraint. We also exploit user tolerance to further curtail the HEVC workload with insignificant video quality degradation. Experimental results illustrate that the proposed approach results in ∼43% power savings on a many-core system.
AB - The High Efficiency Video Coding (HEVC) standard aims at providing ∼50% better compression compared to its predecessor (H.264) at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this work, we present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions (i.e. so-called video tiles) which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced (through dynamically scaling the operating frequency) under a given frame-rate constraint. We also exploit user tolerance to further curtail the HEVC workload with insignificant video quality degradation. Experimental results illustrate that the proposed approach results in ∼43% power savings on a many-core system.
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U2 - 10.7873/DATE2014.232
DO - 10.7873/DATE2014.232
M3 - Conference contribution
AN - SCOPUS:84903829045
SN - 9783981537024
T3 - Proceedings -Design, Automation and Test in Europe, DATE
BT - Proceedings - Design, Automation and Test in Europe, DATE 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th Design, Automation and Test in Europe, DATE 2014
Y2 - 24 March 2014 through 28 March 2014
ER -