Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing

Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The High Efficiency Video Coding (HEVC) standard aims at providing ∼50% better compression compared to its predecessor (H.264) at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this work, we present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions (i.e. so-called video tiles) which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced (through dynamically scaling the operating frequency) under a given frame-rate constraint. We also exploit user tolerance to further curtail the HEVC workload with insignificant video quality degradation. Experimental results illustrate that the proposed approach results in ∼43% power savings on a many-core system.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783981537024
DOIs
StatePublished - 2014
Event17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
Duration: Mar 24 2014Mar 28 2014

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other17th Design, Automation and Test in Europe, DATE 2014
CountryGermany
CityDresden
Period3/24/143/28/14

ASJC Scopus subject areas

  • Engineering(all)

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