Space and time compaction schemes for embedded cores

Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os. We outline an aliasing-free space and time compaction scheme, for both combinational and sequential cores, which minimizes the required test bandwidth and reduces the bandwidth consumption of the Test Access Mechanism at the core output side. The experimental results show that the test bandwidth gain is achieved with no appreciable increase in test application time.