Split manufacturing

Siddharth Garg, Jeyavijayan J.V. Rajendran

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

This chapter discusses split manufacturing, a promising hardware obfuscation technique that partitions a chip into two or more parts, each fabricated at a separate foundry. No one foundry sees the entire design, hindering its ability to thieve the chip’s IP or (as we discuss) maliciously modify the chip. Building upon this intuitive idea, this chapter describes relevant threat models for split manufacturing, a quantitative notion of security for split manufacturing, and techniques to trade off “cost” for security.

Original languageEnglish (US)
Title of host publicationHardware Protection through Obfuscation
PublisherSpringer International Publishing
Pages243-262
Number of pages20
ISBN (Electronic)9783319490199
ISBN (Print)9783319490182
DOIs
StatePublished - Jan 1 2017

Keywords

  • 3D integration
  • BEOL
  • FEOL
  • Hardware trojan
  • IP piracy
  • K-security
  • Proximity attack
  • Secure layout
  • Secure partitioning
  • Split manufacturing
  • Sub-graph isomorphism

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

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