Split manufacturing

Siddharth Garg; Jeyavijayan J.V. Rajendran

doi:10.1007/978-3-319-49019-9_10

Split manufacturing

Siddharth Garg, Jeyavijayan J.V. Rajendran

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This chapter discusses split manufacturing, a promising hardware obfuscation technique that partitions a chip into two or more parts, each fabricated at a separate foundry. No one foundry sees the entire design, hindering its ability to thieve the chip’s IP or (as we discuss) maliciously modify the chip. Building upon this intuitive idea, this chapter describes relevant threat models for split manufacturing, a quantitative notion of security for split manufacturing, and techniques to trade off “cost” for security.

Original language	English (US)
Title of host publication	Hardware Protection through Obfuscation
Publisher	Springer International Publishing
Pages	243-262
Number of pages	20
ISBN (Electronic)	9783319490199
ISBN (Print)	9783319490182
DOIs	https://doi.org/10.1007/978-3-319-49019-9_10
State	Published - Jan 1 2017

Keywords

3D integration
BEOL
FEOL
Hardware trojan
IP piracy
K-security
Proximity attack
Secure layout
Secure partitioning
Split manufacturing
Sub-graph isomorphism

ASJC Scopus subject areas

General Engineering
General Computer Science

Access to Document

10.1007/978-3-319-49019-9_10

Cite this

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Split manufacturing

Abstract

Keywords

ASJC Scopus subject areas

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