SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation

Edward Jongyoon Choi; Injun Choi; Chanhee Jeon; Gichan Yun; Donghyeon Yi; Sohmyung Ha; Ik Joon Chang; Minkyu Je

doi:10.1109/LSSC.2022.3206416

SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation

Edward Jongyoon Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, Sohmyung Ha, Ik Joon Chang, Minkyu Je

Research output: Contribution to journal › Article › peer-review

Abstract

In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient 'one-step' method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.

Original language	English (US)
Pages (from-to)	234-237
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	5
DOIs	https://doi.org/10.1109/LSSC.2022.3206416
State	Published - 2022

Keywords

Charge domain computation
computing-in-Memory (CIM)
convolutional neural network (CNN)
mixed-signal computation
static random-access memory (SRAM)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/LSSC.2022.3206416

Cite this

@article{c464bdfb52124e4b8b0c1d47c8067089,

title = "SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation",

abstract = "In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient 'one-step' method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.",

keywords = "Charge domain computation, computing-in-Memory (CIM), convolutional neural network (CNN), mixed-signal computation, static random-access memory (SRAM)",

author = "Choi, {Edward Jongyoon} and Injun Choi and Chanhee Jeon and Gichan Yun and Donghyeon Yi and Sohmyung Ha and Chang, {Ik Joon} and Minkyu Je",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2022",

doi = "10.1109/LSSC.2022.3206416",

language = "English (US)",

volume = "5",

pages = "234--237",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation

AU - Choi, Edward Jongyoon

AU - Choi, Injun

AU - Jeon, Chanhee

AU - Yun, Gichan

AU - Yi, Donghyeon

AU - Ha, Sohmyung

AU - Chang, Ik Joon

AU - Je, Minkyu

PY - 2022

Y1 - 2022

N2 - In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient 'one-step' method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.

AB - In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient 'one-step' method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.

KW - Charge domain computation

KW - computing-in-Memory (CIM)

KW - convolutional neural network (CNN)

KW - mixed-signal computation

KW - static random-access memory (SRAM)

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JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

ER -

SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation

Abstract

Keywords

ASJC Scopus subject areas

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