Static transition probability analysis under uncertainty

Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam

Research output: Contribution to journalConference articlepeer-review


Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progressive scaling down of feature sizes, the variations in process parameters increase, thereby increasing the uncertainty in gate delay. In this work, we propose a novel non-simulative scheme to compute the transition probability waveforms (TPWs) in a single pass of the circuit for continuous gate delay distributions. These TPWs are continuous functions of time as opposed to the deterministic delay case where transitions are constrained to occur at discrete time points. The TPWs are then used to calculate the dynamic power dissipation in a circuit. We show that the corresponding power estimates obtained from deterministic delay models can be off by as much as 75%. Our method has an average error of only 6% and a speed up of 232× when compared to logic simulations. Another important application of our TPWs is in the area of crosstalk noise where the likelihood of signals switching within a certain timing window is required.

Original languageEnglish (US)
Pages (from-to)380-386
Number of pages7
JournalProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
StatePublished - 2004
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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