Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations

Da Cheng Juan, Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98% accuracy, (2) a 4-tier 3D implementation can be more than 40°C hotter than its 2D counterpart and (3) the proposed tier-stacking algorithm significantly improves the thermal yield from 44.4% to 81.1% for a 3D CMP.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Pages383-388
Number of pages6
StatePublished - 2011
Event14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 - Grenoble, France
Duration: Mar 14 2011Mar 18 2011

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
CountryFrance
CityGrenoble
Period3/14/113/18/11

Keywords

  • 3D
  • chip-multiprocessor
  • leakage
  • process variation
  • regression
  • stack
  • statistical learning
  • thermal
  • yield

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Juan, D. C., Garg, S., & Marculescu, D. (2011). Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 (pp. 383-388). [5763067] (Proceedings -Design, Automation and Test in Europe, DATE).