Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

A. Khakifirooz, K. Cheng, T. Nagumo, N. Loubet, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H. He, P. Kulkarni, Q. Liu, P. Hashemi, P. Khare, S. Luning, S. Mehta, J. Gimbert, Y. Zhu, Z. ZhuJ. Li, A. Madan, T. Levin, F. Monsieur, T. Yamamoto, S. Naczas, S. Schmitz, S. Holmes, C. Aulnette, N. Daval, W. Schwarzenbach, B. Y. Nguyen, V. Paruchuri, M. Khare, G. Shahidi, B. Doris

Research output: Chapter in Book/Report/Conference proceedingConference contribution


High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I eff of 0.95mA/μm and 0.70mA/μm at I off =100nA/μm and V DD of 1V, for NFET and PFET, respectively.

Original languageEnglish (US)
Title of host publication2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Number of pages2
StatePublished - 2012
Event2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
Duration: Jun 12 2012Jun 14 2012

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562


Other2012 Symposium on VLSI Technology, VLSIT 2012
Country/TerritoryUnited States
CityHonolulu, HI

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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