Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

A. Khakifirooz; K. Cheng; T. Nagumo; N. Loubet; T. Adam; A. Reznicek; J. Kuss; D. Shahrjerdi; R. Sreenivasan; S. Ponoth; H. He; P. Kulkarni; Q. Liu; P. Hashemi; P. Khare; S. Luning; S. Mehta; J. Gimbert; Y. Zhu; Z. Zhu; J. Li; A. Madan; T. Levin; F. Monsieur; T. Yamamoto; S. Naczas; S. Schmitz; S. Holmes; C. Aulnette; N. Daval; W. Schwarzenbach; B. Y. Nguyen; V. Paruchuri; M. Khare; G. Shahidi; B. Doris

doi:10.1109/VLSIT.2012.6242489

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

A. Khakifirooz, K. Cheng, T. Nagumo, N. Loubet, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H. He, P. Kulkarni, Q. Liu, P. Hashemi, P. Khare, S. Luning, S. Mehta, J. Gimbert, Y. Zhu, Z. ZhuJ. Li, A. Madan, T. Levin, F. Monsieur, T. Yamamoto, S. Naczas, S. Schmitz, S. Holmes, C. Aulnette, N. Daval, W. Schwarzenbach, B. Y. Nguyen, V. Paruchuri, M. Khare, G. Shahidi, B. Doris

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I _eff of 0.95mA/μm and 0.70mA/μm at I _off =100nA/μm and V _DD of 1V, for NFET and PFET, respectively.

Original language	English (US)
Title of host publication	2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages	117-118
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2012.6242489
State	Published - 2012
Event	2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States Duration: Jun 12 2012 → Jun 14 2012

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2012 Symposium on VLSI Technology, VLSIT 2012
Country/Territory	United States
City	Honolulu, HI
Period	6/12/12 → 6/14/12

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/VLSIT.2012.6242489

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Khakifirooz, A., Cheng, K., Nagumo, T., Loubet, N., Adam, T., Reznicek, A., Kuss, J., Shahrjerdi, D., Sreenivasan, R., Ponoth, S., He, H., Kulkarni, P., Liu, Q., Hashemi, P., Khare, P., Luning, S., Mehta, S., Gimbert, J., Zhu, Y., ... Doris, B. (2012). Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. In 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers (pp. 117-118). Article 6242489 (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2012.6242489

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. / Khakifirooz, A.; Cheng, K.; Nagumo, T. et al.
2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. 2012. p. 117-118 6242489 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Khakifirooz, A, Cheng, K, Nagumo, T, Loubet, N, Adam, T, Reznicek, A, Kuss, J, Shahrjerdi, D, Sreenivasan, R, Ponoth, S, He, H, Kulkarni, P, Liu, Q, Hashemi, P, Khare, P, Luning, S, Mehta, S, Gimbert, J, Zhu, Y, Zhu, Z, Li, J, Madan, A, Levin, T, Monsieur, F, Yamamoto, T, Naczas, S, Schmitz, S, Holmes, S, Aulnette, C, Daval, N, Schwarzenbach, W, Nguyen, BY, Paruchuri, V, Khare, M, Shahidi, G & Doris, B 2012, Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. in 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers., 6242489, Digest of Technical Papers - Symposium on VLSI Technology, pp. 117-118, 2012 Symposium on VLSI Technology, VLSIT 2012, Honolulu, HI, United States, 6/12/12. https://doi.org/10.1109/VLSIT.2012.6242489

@inproceedings{29109ac27f6f401a88b5666cb721a171,

title = "Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS",

abstract = "High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I eff of 0.95mA/μm and 0.70mA/μm at I off =100nA/μm and V DD of 1V, for NFET and PFET, respectively.",

author = "A. Khakifirooz and K. Cheng and T. Nagumo and N. Loubet and T. Adam and A. Reznicek and J. Kuss and D. Shahrjerdi and R. Sreenivasan and S. Ponoth and H. He and P. Kulkarni and Q. Liu and P. Hashemi and P. Khare and S. Luning and S. Mehta and J. Gimbert and Y. Zhu and Z. Zhu and J. Li and A. Madan and T. Levin and F. Monsieur and T. Yamamoto and S. Naczas and S. Schmitz and S. Holmes and C. Aulnette and N. Daval and W. Schwarzenbach and Nguyen, {B. Y.} and V. Paruchuri and M. Khare and G. Shahidi and B. Doris",

year = "2012",

doi = "10.1109/VLSIT.2012.6242489",

language = "English (US)",

isbn = "9781467308458",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "117--118",

booktitle = "2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers",

note = "2012 Symposium on VLSI Technology, VLSIT 2012 ; Conference date: 12-06-2012 Through 14-06-2012",

}

TY - GEN

T1 - Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

AU - Khakifirooz, A.

AU - Cheng, K.

AU - Nagumo, T.

AU - Loubet, N.

AU - Adam, T.

AU - Reznicek, A.

AU - Kuss, J.

AU - Shahrjerdi, D.

AU - Sreenivasan, R.

AU - Ponoth, S.

AU - He, H.

AU - Kulkarni, P.

AU - Liu, Q.

AU - Hashemi, P.

AU - Khare, P.

AU - Luning, S.

AU - Mehta, S.

AU - Gimbert, J.

AU - Zhu, Y.

AU - Zhu, Z.

AU - Li, J.

AU - Madan, A.

AU - Levin, T.

AU - Monsieur, F.

AU - Yamamoto, T.

AU - Naczas, S.

AU - Schmitz, S.

AU - Holmes, S.

AU - Aulnette, C.

AU - Daval, N.

AU - Schwarzenbach, W.

AU - Nguyen, B. Y.

AU - Paruchuri, V.

AU - Khare, M.

AU - Shahidi, G.

AU - Doris, B.

PY - 2012

Y1 - 2012

N2 - High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I eff of 0.95mA/μm and 0.70mA/μm at I off =100nA/μm and V DD of 1V, for NFET and PFET, respectively.

AB - High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I eff of 0.95mA/μm and 0.70mA/μm at I off =100nA/μm and V DD of 1V, for NFET and PFET, respectively.

UR - http://www.scopus.com/inward/record.url?scp=84866546880&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866546880&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2012.6242489

DO - 10.1109/VLSIT.2012.6242489

M3 - Conference contribution

AN - SCOPUS:84866546880

SN - 9781467308458

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 117

EP - 118

BT - 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers

T2 - 2012 Symposium on VLSI Technology, VLSIT 2012

Y2 - 12 June 2012 through 14 June 2012

ER -

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

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