Switch level hot-carrier reliability enhancement of VLSI circuits

Aurobindo Dasgupta, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Long-term reliability of MOS VLSI circuits is becoming an important issue with rapid advances in VLSI technology and increasing VLSI chip densities. Hot-carrier effects and electromigration are the two important failure mechanisms that significantly impact the long-term reliability of high-density VLSI ICs. In this paper, we present a probabilistic switch-level method for identifying MOSFETs in the circuit that are most susceptible to hot-carrier effects. Subsequently, we outline two techniques - (i) reordering of inputs to logic gates and (ii) selective MOSFET sizing - to reduce the hot-carrier susceptibility of these critical MOSFETs. Finally, we show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption. The algorithms are incorporated into SIS and are evaluated on the ISCAS-MCNC91 benchmark suite.

Original languageEnglish (US)
Title of host publicationIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
PublisherIEEE
Pages63-71
Number of pages9
StatePublished - 1995
EventProceedings of the 1995 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, DFT'95 - Lafayette, LA, USA
Duration: Nov 13 1995Nov 15 1995

Other

OtherProceedings of the 1995 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, DFT'95
CityLafayette, LA, USA
Period11/13/9511/15/95

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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