Abstract
Reducing the error detection latency is critical for improving the design visibility while searching for design errors. This article uses a FAQ format to discuss the key points of the symbolic QED method that can be applied during both pre-silicon and post-silicon validation.
Original language | English (US) |
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Article number | 7511763 |
Pages (from-to) | 55-62 |
Number of pages | 8 |
Journal | IEEE Design and Test |
Volume | 33 |
Issue number | 6 |
DOIs | |
State | Published - Dec 2016 |
Keywords
- Debug
- Post-Silicon Validation
- Pre-silicon verification
- Symbolic Quick Error Detection
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering