Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions

Eshan Singh, David Lin, Clark Barrett, Subhasish Mitra

Research output: Contribution to journalArticle

Abstract

Reducing the error detection latency is critical for improving the design visibility while searching for design errors. This article uses a FAQ format to discuss the key points of the symbolic QED method that can be applied during both pre-silicon and post-silicon validation.

Original languageEnglish (US)
Article number7511763
Pages (from-to)55-62
Number of pages8
JournalIEEE Design and Test
Volume33
Issue number6
DOIs
StatePublished - Dec 2016

Keywords

  • Debug
  • Post-Silicon Validation
  • Pre-silicon verification
  • Symbolic Quick Error Detection

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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