Synthesis of fault-tolerant and real-time microarchitectures

Microarchitectural implementations of real-time signal-processing algorithms for mission-critical applications (such as sensors on spacecrafts) are characterized by two unique requirements: real-time processing of a steady stream of input signals, which requires a high-performance implementation such as pipelining, and reliable operation over the mission lifetime, which mandates support for fault tolerance. We relate high-performance and fault-tolerance constraints to chip area and present a methodology for synthesizing area-efficient microarchitectures satisfying these requirements. High performance is achieved via pipelining, whereas desired fault tolerance is realized using hardware redundancy. The framework has been used to synthesize high-performance and fault-tolerant microarchitectures for a variety of signal-processing algorithms. Additionally, the framework has been used to explore design trade-offs between high-performance and high-reliability microarchitectures, subject to a maximum area constraint.