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System-level leakage variability mitigation for MPSoC platforms using body-bias islands
Siddharth Garg
, Diana Marculescu
Electrical and Computer Engineering
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peer-review
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Keyphrases
Variability Mitigation
100%
Body Bias
100%
Multi-processor System-on-chip (MPSoC)
100%
Leakage Power
60%
Adaptive Body Biasing
60%
Bias Voltage
40%
Body Bias Technique
20%
Proposed Methodology
20%
Clock Frequency
20%
Mitigation Techniques
20%
Global Clock
20%
Multiprocessor Systems
20%
Manufacturing Variations
20%
Gate Level
20%
Time Partitioning
20%
Engineering
Energy Dissipation
100%
Bias Voltage
66%
Design Time
66%
Multiprocessor System
33%
Process Variation
33%
Processing Element
33%
Clock Frequency
33%
Manufacturing Process
33%
Computer Science
Leakage Power Dissipation
100%
Clock Frequency
33%
And Gate
33%
Multiprocessor System
33%
Individual Body
33%
Process Variation
33%