TY - GEN
T1 - TailoredCore
T2 - 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021
AU - Gonzalez-Gomez, Jeferson
AU - Avila-Ardon, Steven
AU - Rojas-Gonzalez, Jonathan
AU - Stephen-Cantillano, Andres
AU - Castro-Godinez, Jorge
AU - Salazar-Garcia, Carlos
AU - Shafique, Muhammad
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/2/21
Y1 - 2021/2/21
N2 - One challenge imposed by ubiquitous computing of embedded systems is the need for power and energy-efficient implementations, particularly because many of them are operated with batteries. In this sense, tailored application-specific processors can meet the resource requirements of a specific application in the most efficient way. In this paper, we present TailoredCore, a design methodology to generate application-specific processors based on a core architecture implementation. This methodology analyzes the application to be executed and produces a customized RISC-V core with the resources required, while reducing the hardware overhead due to, for instance, instructions and registers not needed. Using TailoredCore, we achieve up to 38% savings in registers and 12% in logic elements when generating cores for five CHStone benchmark applications and implementing them on an FPGA. These savings in the area also correspond to a reduction of the required power and energy.
AB - One challenge imposed by ubiquitous computing of embedded systems is the need for power and energy-efficient implementations, particularly because many of them are operated with batteries. In this sense, tailored application-specific processors can meet the resource requirements of a specific application in the most efficient way. In this paper, we present TailoredCore, a design methodology to generate application-specific processors based on a core architecture implementation. This methodology analyzes the application to be executed and produces a customized RISC-V core with the resources required, while reducing the hardware overhead due to, for instance, instructions and registers not needed. Using TailoredCore, we achieve up to 38% savings in registers and 12% in logic elements when generating cores for five CHStone benchmark applications and implementing them on an FPGA. These savings in the area also correspond to a reduction of the required power and energy.
KW - ASIP
KW - Design automation
KW - RISC-V
KW - design tools
KW - microprocessors
UR - http://www.scopus.com/inward/record.url?scp=85113931548&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85113931548&partnerID=8YFLogxK
U2 - 10.1109/LASCAS51355.2021.9459152
DO - 10.1109/LASCAS51355.2021.9459152
M3 - Conference contribution
AN - SCOPUS:85113931548
T3 - 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021
BT - 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 February 2021 through 25 February 2021
ER -