TAO: Techniques for algorithm-level obfuscation during high-level synthesis

Christian Pilato, Francesco Regazzoni, Ramesh Karri, Siddharth Garg

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Intellectual Property (IP) theft costs semiconductor design companies billions of dollars every year. Unauthorized IP copies start from reverse engineering the given chip. Existing techniques to protect against IP theft aim to hide the IC's functionality, but focus on manipulating the HDL descriptions. We propose TAO as a comprehensive solution based on high-level synthesis to raise the abstraction level and apply algorithmic obfuscation automatically. TAO includes several transformations that make the component hard to reverse engineer during chip fabrication, while a key is later inserted to unlock the functionality. Finally, this is a promising approach to obfuscate large-scale designs despite the hardware overhead needed to implement the obfuscation.

Original languageEnglish (US)
Title of host publicationProceedings of the 55th Annual Design Automation Conference, DAC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781450357005
DOIs
StatePublished - Jun 24 2018
Event55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: Jun 24 2018Jun 29 2018

Publication series

NameProceedings - Design Automation Conference
VolumePart F137710
ISSN (Print)0738-100X

Other

Other55th Annual Design Automation Conference, DAC 2018
CountryUnited States
CitySan Francisco
Period6/24/186/29/18

Keywords

  • Algorithm-Level Obfuscation
  • High-Level Synthesis
  • IP theft
  • Reverse Engineering

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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  • Cite this

    Pilato, C., Regazzoni, F., Karri, R., & Garg, S. (2018). TAO: Techniques for algorithm-level obfuscation during high-level synthesis. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 [a155] (Proceedings - Design Automation Conference; Vol. Part F137710). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3196126