TY - JOUR
T1 - Terahertz Band Intra-Chip Communications
T2 - Can Wireless Links Scale Modern x86 CPUs?
AU - Petrov, Vitaly
AU - Moltchanov, Dmitri
AU - Komar, Maria
AU - Antonov, Alexander
AU - Kustarev, Pavel
AU - Rakheja, Shaloo
AU - Koucheryavy, Yevgeni
N1 - Funding Information:
This work was supported by the Academy of Finland FiDiPro Program Nanocommunication Networks 2012–2016. The work of V. Petrov was supported by the Nokia Foundation. The work of S. Rakheja was supported by the National Science Foundation under Grant CCF-1565656.
Publisher Copyright:
© 2013 IEEE.
PY - 2017
Y1 - 2017
N2 - Massive multi-core processing has recently attracted significant attention from the research community as one of the feasible solutions to satisfy constantly growing performance demands. However, this evolution path is nowadays hampered by the complexity and limited scalability of bus-oriented intra-chip communications infrastructure. The latest advantages of terahertz (THz) band wireless communications providing extraordinary capacity at the air interface offer a promising alternative to conventional wired solutions for intra-chip communications. Still, to invest resources in this field manufacturers need a clear vision of what are the performance and scalability gains of wireless intra-chip communications. Using the comprehensive hybrid methodology combining THz ray-tracing, direct CPU traffic measurements, and cycle-accurate CPU simulations, we perform the scalability study of x86 CPU design that is backward compatible with the current x86 architecture. We show that preserving the current cache coherence protocols mapped into the star wireless communications topology that allows for tight centralized medium access control a few hundreds of active cores can be efficiently supported without any notable changes in the x86 CPU logic. This important outcome allows for incremental development, where THz-assisted x86 CPU with a few dozens of cores can serve as an intermediate solution, while the truly massive multi-core system with broadcast-enabled medium access and enhanced cache coherence protocols can be an ultimate goal.
AB - Massive multi-core processing has recently attracted significant attention from the research community as one of the feasible solutions to satisfy constantly growing performance demands. However, this evolution path is nowadays hampered by the complexity and limited scalability of bus-oriented intra-chip communications infrastructure. The latest advantages of terahertz (THz) band wireless communications providing extraordinary capacity at the air interface offer a promising alternative to conventional wired solutions for intra-chip communications. Still, to invest resources in this field manufacturers need a clear vision of what are the performance and scalability gains of wireless intra-chip communications. Using the comprehensive hybrid methodology combining THz ray-tracing, direct CPU traffic measurements, and cycle-accurate CPU simulations, we perform the scalability study of x86 CPU design that is backward compatible with the current x86 architecture. We show that preserving the current cache coherence protocols mapped into the star wireless communications topology that allows for tight centralized medium access control a few hundreds of active cores can be efficiently supported without any notable changes in the x86 CPU logic. This important outcome allows for incremental development, where THz-assisted x86 CPU with a few dozens of cores can serve as an intermediate solution, while the truly massive multi-core system with broadcast-enabled medium access and enhanced cache coherence protocols can be an ultimate goal.
KW - CPU design
KW - massive multi-core
KW - medium access control
KW - terahertz band
KW - wireless intra-chip communications
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U2 - 10.1109/ACCESS.2017.2689077
DO - 10.1109/ACCESS.2017.2689077
M3 - Article
AN - SCOPUS:85027971953
SN - 2169-3536
VL - 5
SP - 6095
EP - 6109
JO - IEEE Access
JF - IEEE Access
M1 - 7891056
ER -