@inproceedings{bb836a2fdf9d416cabcc7cc453aae822,
title = "Test power reduction through minimization of scan chain transitions",
abstract = "Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.",
keywords = "Automatic test pattern generation, Circuit testing, Costs, Degradation, Frequency, Logic testing, Power dissipation, Switching circuits, System testing, System-on-a-chip",
author = "O. Sinanoglu and I. Bayraktaroglu and A. Orailoglu",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 20th IEEE VLSI Test Symposium, VTS 2002 ; Conference date: 28-04-2002 Through 02-05-2002",
year = "2002",
doi = "10.1109/VTS.2002.1011129",
language = "English (US)",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
pages = "166--171",
booktitle = "Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002",
}