Test power reduction through minimization of scan chain transitions

O. Sinanoglu, I. Bayraktaroglu, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

Original languageEnglish (US)
Title of host publicationProceedings - 20th IEEE VLSI Test Symposium, VTS 2002
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)0769515703
StatePublished - 2002
Event20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States
Duration: Apr 28 2002May 2 2002

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other20th IEEE VLSI Test Symposium, VTS 2002
Country/TerritoryUnited States


  • Automatic test pattern generation
  • Circuit testing
  • Costs
  • Degradation
  • Frequency
  • Logic testing
  • Power dissipation
  • Switching circuits
  • System testing
  • System-on-a-chip

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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