Test power reduction via deterministic alignment of stimulus and response bits

Keyphrases

• Test Power 100%
• Don't Care Bits 100%
• Test Power Reduction 100%
• On chip 50%
• Scan Architecture 50%
• Stimuli-responsiveness 50%
• Power Dissipation 50%
• Combinational Logic 50%
• Reducing Power 50%
• Scan Cell 50%
• Switching Activity 50%
• Filling Process 50%
• Toggle 50%
• Power Issue 50%
• Test Data Volume 50%
• Capture Power 50%
• On-Chip Decompressor 50%
• Complementary Value 50%
• Scan Slice 50%

Engineering

• Experimental Result 100%
• Test Data 100%
• Energy Dissipation 100%
• Data Volume 100%
• Bit Value 100%
• Switching Activity 100%
• Reducing Power 100%

Computer Science

• Experimental Result 100%
• Power Dissipation 100%
• Combinational Logic 100%
• Independent Set 100%
• Switching Activity 100%
• Test Data Volume 100%