The ATM Layer Chip: An ASIC for B-ISDN Applications

Cesar A. Johnston, H. Jonathan Chao

Research output: Contribution to journalArticlepeer-review

Abstract

This paper describes the architecture of an experimental research prototype application specific integrated circuit (ASIC) designed to serve as a generic building block of the future broadband ISDN (B-ISDN). The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A new media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip interfaces to the B-ISDN through a SONET STS-3c framer chip. The ATM layer chip has been designed using 1.2 pm CMOS technology with a die area of 5.4 × 5.4 mm2 and approximately 27 000 transistors. Experimental results are described. At the user network interface, a chip with the functionality studied in this research prototype can be used to implement broadband terminal adaptors and the network termination. At the broadband local exchange, such a chip can be used in the implementation of ATM statistical multiplexers, ATM switch port controllers, etc.

Original languageEnglish (US)
Pages (from-to)741-750
Number of pages10
JournalIEEE Journal on Selected Areas in Communications
Volume9
Issue number5
DOIs
StatePublished - Jun 1991

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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