The Impact of Logic Locking on Confidentiality: An Automated Evaluation

Lennart M. Reimann, Evgenii Rezunov, Dominik Germek, Luca Collini, Christian Pilato, Ramesh Karri, Rainer Leupers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Logic locking secures hardware designs in untrusted foundries by incorporating key-driven gates to obscure the original blueprint. While this method safeguards the integrated circuit from malicious alterations during fabrication, its influence on data confidentiality during runtime has been ignored. In this study, we employ path sensitization to formally examine the impact of logic locking on confidentiality. By applying three representative logic locking mechanisms on open-source cryptographic benchmarks, we utilize an automatic test pattern generation framework to evaluate the effect of locking on cryptographic encryption keys and sensitive data signals. Our analysis reveals that logic locking can inadvertently cause sensitive data leakage when incorrect logic locking keys are used. We show that a single malicious logic locking key can expose over 70% of an encryption key. If an adversary gains control over other inputs, the entire encryption key can be compromised. This research uncovers a significant security vulnerability in logic locking and emphasizes the need for comprehensive security assessments that extend beyond key-recovery attacks.

Original languageEnglish (US)
Title of host publicationProceedings of the 26th International Symposium on Quality Electronic Design, ISQED 2025
PublisherIEEE Computer Society
ISBN (Electronic)9798331509422
DOIs
StatePublished - 2025
Event26th International Symposium on Quality Electronic Design, ISQED 2025 - Hybrid, San Francisco, United States
Duration: Apr 23 2025Apr 25 2025

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference26th International Symposium on Quality Electronic Design, ISQED 2025
Country/TerritoryUnited States
CityHybrid, San Francisco
Period4/23/254/25/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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