Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chIPs

Heba Khdr, Santiago Pagani, Muhammad Shafique, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In dark silicon chIPs, a significant amount of on-chIP resources cannot be simultaneously powered on and need to stay dark, i.e., power gated, in order to avoid thermal emergencies. This paper presents a resource management technique, called DsRem, that selects the number of active cores jointly with their voltage/frequency (v/f) levels, considering the high Instruction Level Parallelism (ILP) or Thread Level Parallelism (TLP) nature of different applications, in order to maximize the overall system performance. DsRem leverages the positioning of dark cores, to efficiently dissIPate the heat generated by the active cores. This facilitates increasing the v/f level of the active cores, which leads to further performance improvement. Compared to state-of-the-art thermal-aware task application mapping, DsRem achieves up to 46% performance gain, while avoiding any thermal emergencies. Additionally, DsRem outperforms the boosting technique with 26%.

Original languageEnglish (US)
Title of host publication2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450335201
DOIs
StatePublished - Jul 24 2015
Event52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States
Duration: Jun 8 2015Jun 12 2015

Publication series

NameProceedings - Design Automation Conference
Volume2015-July
ISSN (Print)0738-100X

Other

Other52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
CountryUnited States
CitySan Francisco
Period6/8/156/12/15

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Fingerprint Dive into the research topics of 'Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chIPs'. Together they form a unique fingerprint.

Cite this