Thwarting timing attacks on NEMS relay based designs

Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


NEMS relay technology is a promising class of emerging devices that offer zero static leakage and hence overcomes the power dissipation issues of deep-submicron CMOS technology devices. As NEMS relay based digital circuits have potentially higher energy-efficiency than those based on CMOS transistors, circuits based on NEMS relay device are worth exploring. However, NEMS relay devices suffer from large delay compared to CMOS technology; Binary Decision Diagram (BDD) based implementation targets to minimize the total circuit delay, fixing this problem. However, such an implementation renders the timing delay of a NEMS based circuit input-dependent, which can be exploited to infer on-chip secret information from delay information. In this presentation, we illustrate these security vulnerabilities and present countermeasures for a recently proposed energy-efficient block cipher Midori128 that has an on-chip secret key that needs to be protected.

Original languageEnglish (US)
Title of host publicationProceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781467384544
StatePublished - May 23 2016
Event34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States
Duration: Apr 25 2016Apr 27 2016

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other34th IEEE VLSI Test Symposium, VTS 2016
Country/TerritoryUnited States
CityLas Vegas


  • Binary decision diagram (BDD)
  • Midori
  • Nanoelectromechanical System (NEMS) relays
  • Security
  • Side-channel attack
  • Timing attack

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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