Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors

Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip, A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability & fault-tolerance are making on-chip fault-tolerance mandatory. Onchip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in lifecritical systems should be secured against all faults. While faultsecurity can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive faultsecure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead.