Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers

Scaling down CMOS technology results in excessive power dissipation issues. Nanoelectromechanical System (NEMS) relay technology is an alternative emerging solution that overcomes the power dissipation limitation of CMOS technology. However, despite its zero static leakage, NEMS relay technology suffers from large delay compared to CMOS technology. Binary Decision Diagram (BDD) based implementations of NEMS relay design targets minimizing the total delay. However, this implementation renders the timing delay of the output of a BDD input-dependent, which is a threat to security-critical applications, such as ciphers. In this paper, we analyze the impact of the input-dependent timing variation on the security of NEMS relay based cipher implementations. We present a generalized timing attack methodology, which is applicable to both Substitution Permutation Network (SPN) as well as Feistel block ciphers. We provide case studies on state-of-the-art SPN cipher candidate Advanced Encryption Standard (AES) and Feistel cipher candidates Camellia and DES. Our attack analysis shows that compact designs with single S-box implementation can be compromised, while parallel S-box implementations possess an inherent resistance against timing attacks. We also propose a cost-effective countermeasure which eliminates the input-dependent timing variation and thwarts all such timing attacks on BDD based implementations of NEMS relay design.