TY - JOUR
T1 - Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers
AU - Mazumdar, Bodhisatwa
AU - Saeed, Samah Mohamed
AU - Ali, Sk Subidh
AU - Sinanoglu, Ozgur
N1 - Funding Information:
OZGUR SINANOGLU earned the BS degrees in electrical and electronics engineering and in com-puter engineering, both from Bogazici University, Turkey in 1999, and the MS and PhD degrees in computer science and engineering from the Univer-sity of California San Diego in 2001 and 2004, respectively. He is an associate professor of electri-cal and computer engineering at New York Univer-sity Abu Dhabi. He has industry experience at TI, IBM, and Qualcomm, and has been with NYU Abu Dhabi since 2010. During his PhD, he received the IBM PhD fellowship award twice. He also received the best paper awards at IEEE VLSI Test Symposium 2011 and ACM Conference on Computer and Communication Security 2013. His research interests include design-for-test, design-for-security, and design-for-trust for VLSI circuits, where he has more than 140 conference and journal papers, and 15 issued and pending US Patents. He has given more than a dozen tutorials on hardware security and trust in leading CAD and test conferences, such as DAC, DATE, ITC, VTS, ETS, ICCD, ISQED, etc. He is serving as a track/topic chair or technical program committee member in about 15 conferences, and as (guest) an associate editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Journal on Emerging Technologies in Computing Systems, Elsevier Microelectronics Journal, Journal of Electronic Testing: Theory and Applications, and IET Computers & Digital Techniques journals. He is the director of the Design-for-Excellence Lab at NYU Abu Dhabi. His recent research in hardware security and trust is being funded by US National Science Foundation, US Department of Defense, Semiconductor Research Corporation, and Mubadala Technology.
Publisher Copyright:
© 2013 IEEE.
PY - 2017/7/1
Y1 - 2017/7/1
N2 - Scaling down CMOS technology results in excessive power dissipation issues. Nanoelectromechanical System (NEMS) relay technology is an alternative emerging solution that overcomes the power dissipation limitation of CMOS technology. However, despite its zero static leakage, NEMS relay technology suffers from large delay compared to CMOS technology. Binary Decision Diagram (BDD) based implementations of NEMS relay design targets minimizing the total delay. However, this implementation renders the timing delay of the output of a BDD input-dependent, which is a threat to security-critical applications, such as ciphers. In this paper, we analyze the impact of the input-dependent timing variation on the security of NEMS relay based cipher implementations. We present a generalized timing attack methodology, which is applicable to both Substitution Permutation Network (SPN) as well as Feistel block ciphers. We provide case studies on state-of-the-art SPN cipher candidate Advanced Encryption Standard (AES) and Feistel cipher candidates Camellia and DES. Our attack analysis shows that compact designs with single S-box implementation can be compromised, while parallel S-box implementations possess an inherent resistance against timing attacks. We also propose a cost-effective countermeasure which eliminates the input-dependent timing variation and thwarts all such timing attacks on BDD based implementations of NEMS relay design.
AB - Scaling down CMOS technology results in excessive power dissipation issues. Nanoelectromechanical System (NEMS) relay technology is an alternative emerging solution that overcomes the power dissipation limitation of CMOS technology. However, despite its zero static leakage, NEMS relay technology suffers from large delay compared to CMOS technology. Binary Decision Diagram (BDD) based implementations of NEMS relay design targets minimizing the total delay. However, this implementation renders the timing delay of the output of a BDD input-dependent, which is a threat to security-critical applications, such as ciphers. In this paper, we analyze the impact of the input-dependent timing variation on the security of NEMS relay based cipher implementations. We present a generalized timing attack methodology, which is applicable to both Substitution Permutation Network (SPN) as well as Feistel block ciphers. We provide case studies on state-of-the-art SPN cipher candidate Advanced Encryption Standard (AES) and Feistel cipher candidates Camellia and DES. Our attack analysis shows that compact designs with single S-box implementation can be compromised, while parallel S-box implementations possess an inherent resistance against timing attacks. We also propose a cost-effective countermeasure which eliminates the input-dependent timing variation and thwarts all such timing attacks on BDD based implementations of NEMS relay design.
KW - AES
KW - Nanoelectromechanical system (NEMS) relays
KW - binary decision diagram (BDD)
KW - security
KW - side-channel attacks
KW - timing attack
UR - http://www.scopus.com/inward/record.url?scp=85030090956&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85030090956&partnerID=8YFLogxK
U2 - 10.1109/TETC.2016.2551044
DO - 10.1109/TETC.2016.2551044
M3 - Article
AN - SCOPUS:85030090956
VL - 5
SP - 317
EP - 328
JO - IEEE Transactions on Emerging Topics in Computing
JF - IEEE Transactions on Emerging Topics in Computing
SN - 2168-6750
IS - 3
M1 - 7447781
ER -