TY - GEN
T1 - Toggle-based masking scheme for clustered unknown response bits
AU - Sinanoglu, Ozgur
PY - 2011
Y1 - 2011
N2 - Masking schemes typically suffer from over-masking of bits that may possess fault effect information, degrading test quality levels. Unknown response bits (x's) exhibit a clustered distribution in responses due to structural proximity of x sources. In this work, we propose a toggle-based masking scheme that is capable of delivering very high observability levels in the case of clustered x distributions. The proposed scheme assigns a single-bit state to each chain, dictating whether the chain will be masked or observed. Clustered distribution of x's enables an infrequent switching of state information, minimizing the amount of mask data that selectively toggles the state of chains. Thus, only a few mask channels are needed to control the proposed masking hardware, enabling the blocking of all x's while over-masking a small number of non-x bits. Capability to mask all x's enables the use of a MISR in conjunction, and thus eliminates the need for any scan-out channels, translating into enhanced parallelism in multi-site testing. Results on industrial test cases show that the proposed masking scheme is capable of minimizing or even eliminating over-masking, delivering near-optimal test quality levels.
AB - Masking schemes typically suffer from over-masking of bits that may possess fault effect information, degrading test quality levels. Unknown response bits (x's) exhibit a clustered distribution in responses due to structural proximity of x sources. In this work, we propose a toggle-based masking scheme that is capable of delivering very high observability levels in the case of clustered x distributions. The proposed scheme assigns a single-bit state to each chain, dictating whether the chain will be masked or observed. Clustered distribution of x's enables an infrequent switching of state information, minimizing the amount of mask data that selectively toggles the state of chains. Thus, only a few mask channels are needed to control the proposed masking hardware, enabling the blocking of all x's while over-masking a small number of non-x bits. Capability to mask all x's enables the use of a MISR in conjunction, and thus eliminates the need for any scan-out channels, translating into enhanced parallelism in multi-site testing. Results on industrial test cases show that the proposed masking scheme is capable of minimizing or even eliminating over-masking, delivering near-optimal test quality levels.
UR - http://www.scopus.com/inward/record.url?scp=80051972320&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80051972320&partnerID=8YFLogxK
U2 - 10.1109/ETS.2011.57
DO - 10.1109/ETS.2011.57
M3 - Conference contribution
AN - SCOPUS:80051972320
SN - 9780769544335
T3 - Proceedings - 16th IEEE European Test Symposium, ETS 2011
SP - 105
EP - 110
BT - Proceedings - 16th IEEE European Test Symposium, ETS 2011
T2 - 16th IEEE European Test Symposium, ETS 2011
Y2 - 23 May 2011 through 27 May 2011
ER -