This paper presents a methodology for designing an approximate coarse- g rained reconfigurable architecture (X-CGRA), and its use for accelerating both error-resilient and error-sensitive applications. The output quality of the X-CGRA is manageable at the run-time for better performance and power/energy consumption tradeoffs. Results show up to 1.9× speedup and 2.3× lower energy consumption at the cost of 9.7% accuracy loss for the studied applications.
- Coarse-Grained Reconfigurable Architecture
- Configurable Accuracy Computing
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering