Networks-on-Chips (NoCs) are meeting the growing inter-tile communication needs of multicore chips. However, achieving system scalability by utilizing hundreds of cores on-chip requires high performance, yet energy-efficient on-chip interconnects. As electrical interconnects are marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, are an alternative attractive solution. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrate's subsurface, a greater portion of a chip's real estate can be utilized by cores and routers, while non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such silicon-in-silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links topology that provides both higher effective throughput and throughput-to-power ratio versus prior-art.