Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition

Logic locking is a promising countermeasure against intellectual property (IP) piracy, counterfeiting, hardware Trojans, reverse engineering, and overbuilding attacks. Yet, various attacks that use a working chip as an oracle have been launched on logic locking, undermining the defense of all existing locking techniques. This paper advances the state-of-the-art in logic locking by developing new countermeasures as well as attacks. We present two logic locking techniques, SARLock and SFLL, that provide quantitative security guarantees against the SAT, removal, and approximate attacks. We validate the effectiveness of proposed techniques by taping-out two silicon chips. We also study the interplay between logic locking and VLSI test, highlighting the security vulnerabilities associated with the test of locked chips. We develop three removal attacks to evaluate the security of existing logic locking techniques.