TY - GEN
T1 - Towards provably-secure performance locking
AU - Zaman, Monir
AU - Sengupta, Abhrajit
AU - Liu, Danqing
AU - Sinanoglu, Ozgur
AU - Makris, Yiorgos
AU - Rajendran, Jeyavijayan J.V.
N1 - Publisher Copyright:
© 2018 EDAA.
PY - 2018/4/19
Y1 - 2018/4/19
N2 - Locking the functionality of an integrated circuit (IC) thwarts attacks such as intellectual property (IP) piracy, hardware Trojans, overbuilding, and counterfeiting. Although functional locking has been extensively investigated, locking the performance of an IC has been little explored. In this paper, we develop provably-secure performance locking, where only on applying the correct key the IC shows superior performance; for an incorrect key, the performance of the IC degrades significantly. This leads to a new business model, where the companies can design a single IC capable of different performances for different users. We develop mathematical definitions of security and theoretically, and experimentally prove the security against the state-of-the-art-attacks. We implemented performance locking on a FabScalar microprocessor, achieving a degradation in instructions per clock cycle (IPC) of up to 77% on applying an incorrect key, with an overhead of 0.6%, 0.2%, and 0% for area, power, and delay, respectively.
AB - Locking the functionality of an integrated circuit (IC) thwarts attacks such as intellectual property (IP) piracy, hardware Trojans, overbuilding, and counterfeiting. Although functional locking has been extensively investigated, locking the performance of an IC has been little explored. In this paper, we develop provably-secure performance locking, where only on applying the correct key the IC shows superior performance; for an incorrect key, the performance of the IC degrades significantly. This leads to a new business model, where the companies can design a single IC capable of different performances for different users. We develop mathematical definitions of security and theoretically, and experimentally prove the security against the state-of-the-art-attacks. We implemented performance locking on a FabScalar microprocessor, achieving a degradation in instructions per clock cycle (IPC) of up to 77% on applying an incorrect key, with an overhead of 0.6%, 0.2%, and 0% for area, power, and delay, respectively.
KW - Boolean satisfiability (SAT)
KW - FabScalar
KW - IP piracy
KW - performance locking
UR - http://www.scopus.com/inward/record.url?scp=85048771054&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048771054&partnerID=8YFLogxK
U2 - 10.23919/DATE.2018.8342269
DO - 10.23919/DATE.2018.8342269
M3 - Conference contribution
AN - SCOPUS:85048771054
T3 - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
SP - 1592
EP - 1597
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
Y2 - 19 March 2018 through 23 March 2018
ER -