High-Level Synthesis (HLS) tools that compile algorithms written in high-level languages into register-transfer level implementations can significantly improve design productivity and lower engineering cost. However, HLS-generated designs still lag handwritten implementations in a number of areas, particularly in the efficient allocation of hardware resources. In this work, we propose the use of dynamic dependence analysis to generate higher quality designs using existing HLS tools. We focus on resource sharing for compute-intensive workloads, a major limitation of relying only on static analysis. We demonstrate that with dynamic dependence analysis, the synthesized designs can achieve an order of magnitude resource reduction without performance loss over the state-of-the-art HLS solutions.
|Title of host publication
|IEEE International Symposium on Circuits and Systems
|Subtitle of host publication
|From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
|Institute of Electrical and Electronics Engineers Inc.
|Published - Sep 25 2017
|50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: May 28 2017 → May 31 2017
|Proceedings - IEEE International Symposium on Circuits and Systems
|50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
|5/28/17 → 5/31/17
ASJC Scopus subject areas
- Electrical and Electronic Engineering